Cyclic redundancy checking (CRC) refers to a manner of detecting errors in data. The data may be in the form of electronic communications, stored data or other electronic data. In either case, a cyclic redundancy check generally operates by generating a “check value” for a block of data. The check value is calculated against the block of data and generally characterizes the data. In other words, the CRC calculation produces the check value as an abbreviated representation of the block of data.
Thus, the integrity of the block of data can be checked by re-calculating the check value and comparing a newly calculated check value with an original check value. When the two check values do not match, then an error has been introduced into the block of data since the original check value was generated. Accordingly, the check value provides a manner of detecting errors introduced into the data from communicating or storing the data.
However, implementing cyclic redundancy checking is a complex task. For example, pipelining sub-processes of a cyclic redundancy check calculation presents difficulties since each step is dependent on a result from a previous step. In other words, because CRC is cyclic and a next calculation depends on a result of a current calculation, pipelining operations in parallel is generally not feasible. Many existing solutions attempt to circumvent this difficulty by using additional circuitry to manipulate the data on the data bus. However, such solutions typically suffer from increased costs associated with increased chip area.
Moreover, as data throughput increases, bus width within associated circuitry also increases, which translates to an increased number of calculations performed in each clock cycle to maintain timing within the circuitry. Prior solutions fail to maintain the timing at these increased bandwidths because of an inability to efficiently process the data. These inefficiencies arise from circuitry in the processing/data path that slows down the propagation of data through the circuit and complicates timing. Consequently, the process of generating and checking CRC values becomes a bottleneck that slows down operation of an associated device. These difficulties are further exaggerated in relation to performing CRC calculations on high throughput data carried over data busses of increasing widths as is becoming more common in advanced communications and storage devices.